FIG. 1 is cross-sectional view schematically showing the structure of a conventional junction field effect transistor. The transistor includes a metal source electrode 1, a metal gate electrode 2, and a metal drain electrode 3. The gate electrode 2 is disposed on a gate region 4 which is a residual portion of a p-type layer 4. Source and drain electrodes 1 and 3 are disposed on an n-type channel layer 6 and form ohmic contacts with that channel layer. Gate region 4 is disposed on channel layer 6 between the source and drain electrodes 1 and 3 and forms a rectifying junction with layer 6. Typically, channel layer 6 is disposed on a buffer layer 8 that is undoped. The entire structure is disposed on a substrate 9, for example, a semi-insulating gallium arsenide substrate when the other materials employed in the JFET are gallium arsenide or aluminum gallium arsenide. The gate region 4 is formed by etching a semiconductor layer that is epitaxially grown, for example, by molecular beam epitaxy (MBE), on channel layer 6. The area of the junction formed between gate region 4 and channel layer 6 is controlled by the amount of etching of the epitaxial layer.
The performance characteristics, particularly the frequency response, of the JFET shown in FIG. 1 is controlled by the area of the junction between gate region 4 and channel layer 6. The cutoff frequency f.sub.T of the JFET when used in an amplifier or the maximum oscillation frequency f.sub.max when the JFET is used in an oscillator are typically better than the cutoff and oscillation frequencies of JFETs formed by ion implantation, as described below. However, control of the etching step forming the junction between gate region 4 and channel layer 6 is difficult so that characteristics of devices intended to be identical but manufactured at different times can be significantly different.
The variability of the characteristics of JFETs having the structure shown in FIG. 1 is illustrated with the aid of the partial, schematic view of FIG. 2. As illustrated in FIG. 2, a channel layer 6 has a width W of 200 microns and the distance 1 between the gate region 4 and the source electrode 1 is one micron. In order to ensure that all of the p-type layer between the source and drain electrodes, except gate region 4, is removed in an etching step, the n-type channel layer 6 is etched and partially removed in the vicinity of the gate region 4. In FIG. 2, the interface between the channel layer 6 and the gate layer 4 before etching is indicated by broken lines and the solid lines indicate the channel layer 6 after etching. Typically, the excessive etching removes 100 to 300 Angstroms of the channel layer. Therefore, the thickness t of the channel varies from approximately 1,000 Angstroms near the source and drain electrodes to as little as 700 Angstroms on opposite sides of the gate region 4. The carrier concentration n of electrons in the channel layer 6 is typically about 1.5.times.10.sup.17 cm.sup.-3 and the electron mobility .mu..sub.e is about 4,000 cm.sup.2 /(V s). The source resistance R is: EQU R=(.rho./t)(1/W)
where .rho. is the resistivity of the material and equals (1/qn.mu..sub.e) and q, the electronic charge, is 1.601.times.10.sup.-19 C. For the typical carrier concentration and mobility, .rho. equals 1.041.times.10.sup.-2 ohm-cm.
When the channel thickness t is a constant 1,000 Angstroms, the source resistance R is 5.2 ohms. However, if the thickness t of the channel is only about 700 Angstroms because of 300 Angstroms of etching into the channel layer, then the source resistance R increases to 7.5 ohms. This change represents a variation of about 44 percent, depending upon the depth of etching of the channel layer. In practical experience, however, the source resistance varies by much more, for example, approximately 100 percent, amongst etched JFETs made by the same process but at different times.
FIG. 3 is a sectional schematic view of the structure of a conventional junction field effect transistor made by ion implantation in a method very similar to that used conventionally for making Schottky barrier field effect transistors in gallium arsenide. In FIG. 3, as in the other figures, the same elements previously described are given the same reference numbers. In the structure shown in FIG. 3, the p-type gate region 4 is disposed within n-type channel layer 6 and lies at a surface where the gate electrode 2 is disposed. The structure of FIG. 3 includes relatively heavily doped n.sup.+ similar or identical source and drain regions 7 and 7' lying below the source and drain electrodes 1 and 3, respectively. In one method of manufacturing this type of JFET, the n-type layer 6 is epitaxially grown or formed by diffusion or ion implantation of impurities. Thereafter, the central portion of the n-type layer 6 is masked against ion implantation and n.sup.+ regions 7 and 7' are produced by ion implantation. Finally, p-type gate region 4 is formed by diffusion or ion implantation employing a mask protecting the area outside the gate region from the p-type dopant ions during implantation or diffusion. The resulting JFET device can be more controllably produced than the structure of FIG. 1 because no etching at a pn junction is required. However, the pn junction that is formed has a parasitic capacitance, in addition to the inherent gate capacitance, reducing the frequency performance of the JFET.
The frequency response characteristics of a field effect transistor are frequently expressed as a cutoff frequency f.sub.T. EQU f.sub.T =(g.sub.m /2.pi.C.sub.gs)
where g.sub.m is the transconductance of the device and C.sub.gs is the capacitance between the gate and source.
The elements of the parasitic capacitance of the structure of FIG. 3 are illustrated in FIGS. 4(a) and 4(b). FIG. 4(a) shows in cross-section the central portion of the JFET of FIG. 3 including the gate region 4 and gate electrode 2. The junction structure is enlarged in FIG. 4(b) and the depletion layer generated at the junction between the p-type gate region and the n-type channel layer 6 is illustrated. The capacitive components of the depletion layer are C'.sub.0 at the deepest part of the junction, parallel to the surface on which the gate electrode 2 is disposed, and C'.sub.f at each of the two sides of the junction that are generally transverse to the surface on which the gate electrode 2 is disposed. These capacitive components are electrically connected in parallel so that the total capacitance is their arithmetic sum, i.e., EQU C.sub.gs =C'.sub.0 +2C'.sub.f.
A specific example of the capacitance of the JFET of FIG. 3 is illustrated in FIG. 5. In that example, the gate length 1, i.e., the length of the gate region between the source and drain electrodes, is 0.5 micron, the channel width is 200 microns, and the depth t of the gate region is 0.1 micron. The capacitive component at each of the transverse sides of the gate region is about one-fifth of the capacitance at the deepest portion of the gate region based on these dimensions. For a transconductance of 200 mS/mm and a capacitance per unit area of 1.0.times.10.sup.-12 F/mm, the cutoff frequency f.sub.T of this prior art structure is approximately 30 GHz. This cutoff frequency is much lower than desired. The JFET structure of FIG. 1 has a lower junction capacitance than the structure of FIG. 3 since there are no lateral components of the junction capacitance in the structure of FIG. 1. As a result, a higher cutoff frequency can be achieved with the JFET structure of FIG. 1.
The foregoing description illustrates that, in the prior art, a choice must be made between repeatability, i.e., consistent JFET characteristics, achieved in manufacturing the planar structure of FIG. 3 and extended high frequency performance achieved in the structure of FIG. 1 having a reduced gate capacitance.